1. Field of the Invention
The present invention relates to an information processor and an information processing method, and more specifically to an information processor and an information processing method that are suitably used for reading data stored in a memory by DMA (Direct Memory Access) and transmitting the read data via a network.
2. Description of the Related Art
A system is considered in which data is transmitted from a transmitter to a receiver via a network. FIG. 1 shows an example of the configuration of the system.
A transmitter 1 includes a CPU 11 for controlling the entire transmitter 1 by executing a predetermined program, a memory 13 connected to the CPU 11 via a data bus 12, a memory controller 14, and a network card 15. The memory 13 stores data to be transmitted to a receiver 3 (hereinafter, referred to as the “transmit data”). Normally, in order that the data does not unnecessarily occupy the CPU 11, the data is read by DMA (Direct Memory Access) from the memory 13 and moved to the network card 15 before being transmitted from the network card 15 to the receiver 3 via a network 2.
Referring to the flowchart of FIG. 2, description will be made of the operation of performing DMA on the network card 15 with respect to the transmit data recorded in the memory 13. In step S1, the CPU 11 writes packet-by-packet information on the transmit data into each descriptor of a descriptor table provided in the memory 13.
FIG. 3 shows an example of the descriptor table. The descriptor table includes a plurality of descriptors #0 through #n recorded in a continuous region of the memory 13. FIG. 4 shows the data structure of each descriptor. Described in the descriptor are “address(high)” indicating the higher 32 bits, “address(low)” indicating the lower 32 bits, “reserved” indicating unused 16 bits, and “length” consisting of 16 bits indicating the packet length, of a recording start address in the memory 13 of the corresponding packet.
Returning to FIG. 2, in step S2, the CPU 11 notifies the network card 15 of the numbers of descriptors that have become usable (that is, descriptors into which the packet-by-packet information has been written through the processing in step S1).
In response to the above notification, in step S3, the network card 15 sequentially reads usable descriptors one by one from the memory 13. Then, in step S4, the network card 15 notifies the memory controller 14 of the recording start address and the packet length that are described in each descriptor. In response to this notification, the memory controller 14 causes data stored in the memory 13 which has the above recording start address at the leading end and the above packet length to be transferred by DMA from the memory 13 to the network card 15. The network card 15 transmits the DMA-transferred packet to the receiver 3 via the network 2. Through the processing of steps S3 and S4, one packet of the transmit data has been moved to the network card 15 and transmitted to the receiver 3.
In step S5, the network card 15 makes a determination as to whether there are descriptors that have not yet been read among the usable descriptors. If it is determined that there are descriptors that have not yet been read, the processing returns to step S3, and the subsequent processing is repeated. If it is determined in step S5 that there are no descriptors that have not been read, it means that all the packets forming the transmit data have been moved to the network card 15 and transmitted to the receiver 3. The processing thus advances to step S6. In step S6, the network card 15 notifies the CPU 11 of the end of DMA. In step S7, the CPU 11 frees up the space on the memory 13 in which the transmit data was recorded. The foregoing completes the description of the operation of performing a DMA transfer from the memory 13 to the network card 15.
Note that DMA transfer is described in, for example, Japanese Unexamined Patent Application Publication No. 2000-298640.